 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| LTC4007-1 4A, High Efficiency, Li-Ion Battery Charger FEATURES DESCRIPTIO Charger Controller for 3- or 4-Cell Lithium-Ion Batteries High Conversion Efficiency: Up to 96% Output Currents Exceeding 4A 0.8% Charging Voltage Accuracy Built-In Charge Termination for Li-Ion Batteries AC Adapter Current Limiting Maximizes Charge Rate* Thermistor Input for Temperature Qualified Charging Wide Input Voltage Range: 6V to 28V 0.5V Dropout Voltage; Maximum Duty Cycle: 98% Programmable Charge Current: 4% Accuracy Indicator Outputs for Charging, C/10 Current Detection, AC Adapter Present, Low Battery, Input Current Limiting and Faults Charging Current Monitor Output Available in a 24-Pin 4mm x 5mm QFN Package The LTC(R)4007-1 is a constant-current/constant-voltage charger controller for 3- or 4-cell lithium-ion batteries. The PWM controller uses a synchronous, quasi-constant frequency, constant off-time architecture that will not generate audible noise even when using ceramic capacitors. Charging current is programmable to 4% accuracy using a programming resistor. Charging current can also be monitored as a voltage across the programming resistor. The output float voltage is pin programmed for cell count (3 cells or 4 cells) and chemistry (4.2V/4.1V). A timer, programmed by an external resistor, sets the total charge time. The LTC4007-1 includes a thermistor input, which suspends charging if an unsafe temperature condition is detected. If the cell voltage is less than 3.25V, a low-battery indicator asserts and can be used to program a trickle charge current to safely charge depleted batteries. The FAULT pin is also asserted and charging terminates if the low-battery condition persists for more than 1/4 of the total charge time. , LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. *Protected by U.S. Patents including 5723970. APPLICATIO S Notebook Computers Portable Instruments Battery-Backup Systems Li-Ion Chargers TYPICAL APPLICATIO DCIN 0V TO 28V 3C4C 100k LOBAT ICL ACP SHDN FAULT CHG FLAG 32.4k 100k 100k CHEM LOBAT ICL ACP SHDN FAULT CHG FLAG NTC THERMISTOR 10k NTC RT 0.47F 309k 12.6V, 4A Li-Ion Battery Charger INPUT SWITCH 0.1F 4.99k VLOGIC DCIN INFET CLP 20F Q1 Q2 10H 0.025 Li-Ion BATTERY 15nF 0.025 SYSTEM LOAD PART LTC4007-1 LTC4007 AUTO RESTART NO YES LOW BATTERY THRESHOLD (Per Cell) (4.2V/4.1V) 3.25V/3.173V 2.5V/2.44V LTC4007-1 CLN TGATE BGATE PGND CSP BAT PROG ITH GND 6.04k 0.12F 0.0047F 26.7k 3.01k 3.01k TIMING RESISTOR (~2 HOURS) Q1: Si4431BDY Q2: FDC645N 40071 TA01 U 20F CHARGING CURRENT MONITOR U U 40071f 1 LTC4007-1 ABSOLUTE MAXIMUM RATINGS (Note 1) PACKAGE/ORDER INFORMATION TOP VIEW Voltage from DCIN, CLP, CLN to GND ....... + 32V/- 0.3V PGND with Respect to GND ................................. 0.3V CSP, BAT to GND ....................................... +28V/- 0.3V CHEM, 3C4C, RT to GND .............................. +7V/- 0.3V NTC ............................................................ +10V/- 0.3V ACP, SHDN, CHG, FLAG, FAULT, LOBAT, ICL .............................................. + 32V/- 0.3V CLP to CLN ........................................................... 0.5V Operating Ambient Temperature Range (Note 4) ............................................. - 40C to 85C Operating Junction Temperature ......... - 40C to 125C Storage Temperature Range ................. - 65C to 125C 24 23 22 21 20 ACP 1 RT 2 FAULT 3 GND 4 3C4C 5 LOBAT 6 NTC 7 8 9 10 11 12 25 19 NC 18 PGND 17 TGATE 16 CLN 15 CLP 14 FLAG 13 CHEM ICL CSP UFD PACKAGE 24-LEAD (4mm x 5mm) PLASTIC QFN TJMAX = 125C, JA = 90C/W EXPOSED PAD (PIN 25), GND AND PGND SHOULD BE CONNECTED TOGETHER WITH A LOW OHMIC CONNECTION. ORDER PART NUMBER LTC4007EUFD-1 PROG UFD PART MARKING 40071 Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS SYMBOL IQ VTOL ITOL PARAMETER DCIN Operating Range Operating Current Charge Voltage Accuracy Charge Current Accuracy (Note 3) The denotes specifications which apply over the full operating temperature range (Note 4), otherwise specifications are at TA = 25C. VDCIN = 20V, VBAT = 12V unless otherwise noted. CONDITIONS Sum of Current from CLP, CLN , DCIN Nominal Values: 12.3V, 12.6V, 16.4V, 16.8V (Note 2) VCSP - VBAT Target = 100mV MIN 6 BAT ITH BGATE SHDN INFET DCIN CHG TYP 3 MAX 28 5 0.8 1.0 4 5 UNITS V mA % % % % % % ms A A V V A mA 40071f -0.8 -1.0 -4 -5 60 35 42 20 -10 4.2 1 4.7 1.6 - 10 2 VBAT < 6V, VCSP - VBAT Target = 10mV 6V VBAT VLOBAT, VCSP - VBAT Target = 10mV TSAMPLE Shutdown Battery Leakage Current UVLO Undervoltage Lockout Threshold Shutdown Threshold at SHDN SHDN Pin Current Operating Current in Shutdown VSHDN = 0V, Sum of Current from CLP, CLN, DCIN DCIN = 0V SHDN = 3V DCIN Rising, VBAT = 0 Measured Sample Time RRT = 1190k 60 35 10 5.5 2.5 3 2 U W U U WW W LTC4007-1 ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER Input Bias Current Into BAT Pin CMSL CMSH ITMAX ITREV CA1/I1 Input Common Mode Low CA1/I1 Input Common Mode High Maximum Current Sense Threshold (VCSP - VBAT) Reverse Current Threshold (VCSP - VBAT) Transconductance Source Current Sink Current Current Limit Amplifier Transconductance VCLP ICLP Current Limit Threshold CLP Input Bias Current Transconductance Sink Current OVSD Overvoltage Shutdown Threshold as a Percent of Programmed Charger Voltage DCIN Detection Threshold (VDCIN - VCLN) Forward Regulation Voltage (VDCIN - VCLN) Reverse Voltage Turn-Off Voltage (VDCIN - VCLN) INFET "On" Clamping Voltage (VDCIN - VINFET) INFET "Off" Clamping Voltage (VDCIN - VINFET) Thermistor NTCVR Reference Voltage During Sample Time High Threshold Low Threshold Thermistor Disable Current Indicator Outputs (ACP, CHG, FLAG, LOBAT, ICL, FAULT C10TOL LBTOL FLAG (C/10) Accuracy LOBAT Threshold Accuracy Current Sense Amplifier, CA1 The denotes specifications which apply over the full operating temperature range (Note 4), otherwise specifications are at TA = 25C. VDCIN = 20V, VBAT = 12V unless otherwise noted. CONDITIONS MIN TYP 11.67 MAX UNITS A V 0 VCLN - 0.2 140 165 -30 1 200 V mV mV mmho A A mmho Current Comparators ICMP and IREV VITH = 2.5V Current Sense Amplifier, CA2 Measured at ITH, VITH = 1.4V Measured at ITH, VITH = 1.4V - 40 40 1.4 93 100 100 1 107 mV nA mmho A Voltage Error Amplifier, EA Measured at ITH, VITH = 1.4V 36 102 107 110 % Input P-Channel FET Driver (INFET) DCIN Voltage Ramping Up from VCLN - 0.1V DCIN Voltage Ramping Down IINFET = 1A IINFET = - 25A 4.5 VNTC Rising VNTC Falling VNTC 10V Voltage Falling at PROG 3C4C = 0V, CHEM = 0V 3C4C = 0V, CHEM = Open 3C4C = Open, CHEM = 0V 3C4C = Open, CHEM = Open 0 0.17 25 0.25 50 6.5 0.25 V mV mV V V V - 60 5 - 25 5.8 NTCVR * 0.48 NTCVR * 0.115 NTCVR * 0.5 NTCVR * 0.125 NTCVR * 0.52 NTCVR * 0.135 10 V V A V V V V V mV 0.375 9.233 9.458 12.311 12.610 83 0.397 9.519 9.750 12.692 13.000 93 0.420 9.805 10.043 13.074 13.390 1O5 ICL Threshold Accuracy 40071f 3 LTC4007-1 ELECTRICAL CHARACTERISTICS SYMBOL VOL VOH IOFF IPO PARAMETER Low Logic Level of ACP, CHG, FLAG, LOBAT, ICL, FAULT High Logic Level of CHG, LOBAT, ICL Off State Leakage Current of ACP, FLAG, FAULT Pull-Up Current on CHG, LOBAT, ICL Timer Defeat Threshold at CHG Programming Inputs (CHEM and 3C4C) VIH VIL IPI Oscillator fOSC fMIN DCMAX Regulator Switching Frequency Regulator Switching Frequency in Drop Out Regulator Maximum Duty Cycle VTGATE High (VCLN - VTGATE) VBGATE High VTGATE Low (VCLN - VTGATE) VBGATE Low TGTR TGTF BGTR BGTF TGATE Transition Time TGATE Rise Time TGATE Fall Time BGATE Transition Time BGATE Rise Time BGATE Fall Time VTGATE at Shutdown (VCLN - VTGATE) VBGATE at Shutdown High Logic Level Low Logic Level Pull-Up Current The denotes specifications which apply over the full operating temperature range (Note 4), otherwise specifications are at TA = 25C. VDCIN = 20V, VBAT = 12V unless otherwise noted. CONDITIONS IOL = 100A IOH = -1A VOH = 3V V = 0V 1 MIN TYP MAX 0.5 UNITS V V 2.7 -1 -10 1 A A V 3.3 1 - 14 255 300 25 99 50 4.5 4.5 5.6 5.6 10 10 50 50 50 40 40 110 100 90 80 100 100 345 V V A kHz kHz % mV V V mV ns ns ns ns mV mV V = 0V Duty Cycle 98% VCSP = VBAT ITGATE = -1mA CLOAD = 3000pF CLOAD = 3000pF IBGATE = 1mA CLOAD = 3000pF, 10% to 90% CLOAD = 3000pF, 10% to 90% CLOAD = 3000pF, 10% to 90% CLOAD = 3000pF, 10% to 90% ITGATE = -1A, DCIN = 0V, CLN = 12V IBGATE = 1A, DCIN = 0V, CLN = 12V 20 98 Gate Drivers (TGATE, BGATE) Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: See Test Circuit. Note 3: Does not include tolerance of current sense resistor or current programming resistor. Note 4: The LTC4007E-1 is guaranteed to meet performance specifications from 0C to 85C. Specifications over the -40C to 85C operating temperature range are assured by design, characterization and correlation with statistical process controls. 40071f 4 LTC4007-1 TYPICAL PERFOR A CE CHARACTERISTICS INFET Response Time to Reverse Current 0.10 Vgs OF PFET (2V/DIV) Vgs = 0 0.05 OUTPUT VOLTAGE ERROR (%) 0 -0.05 VOUT ERROR (%) -0.10 -0.15 -0.20 -0.25 -0.30 Id (REVERSE) OF PFET (5A/DIV) Id = 0A 1.25s/DIV TEST PERFORMED ON DEMOBOARD VCHARGE = 12.6V VIN = 15VDC CHARGER = ON PFET = 1/2 Si4925DY ICHARGE = <10mA 40071 G01 -0.35 -0.40 -0.45 13 15 17 19 21 23 25 VDCIN (V) 27 29 31 C3C4 = GND C3C4 = OPEN Vs OF PFET (5V/DIV) Vs = 0V PWM Frequency vs Duty Cycle 350 300 PWM FREQUENCY (kHz) 250 200 150 PROGRAMMED CURRENT = 10% 100 50 0 0 DCIN = 15V DCIN = 20V DCIN = 24V 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 DUTY CYCLE (VOUT/VIN) 40071 G04 1A Load Step (Battery Not Present) 40 BATTERY LEAKAGE CURRENT (A) CHARGER CURRENT (500mA/DIV) OUTPUT VOLTAGE (5V/DIV) DCIN = 20V VFLOAT = 12.6V 40071 G07 UW Line Regulation 0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0 VOUT vs IOUT 3C4C = GND 3C4C = OPEN 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 OUTPUT CURRENT (A) 40071 G03 40071 G02 Disconnect/Reconnect Battery (Load Dump) 3A STEP 1A Load Step (Battery Present) CHARGER CURRENT (1A/DIV) 1A STEP VFLOAT 1V/DIV 1A STEP OUTPUT VOLTAGE (500mV/DIV) LOAD STATE 3A STEP DISCONNECT RECONNECT LOAD CURRENT = 1A, 2A, 3A DCIN = 20V VFLOAT = 12.6V (3C4C = GND, CHEM = OPEN) 40071 G05 DCIN = 20V VFLOAT = 12.6V 40071 G06 Battery Leakage Current vs Battery Voltage VDCIN = 0V 35 30 25 20 15 10 5 0 0 5 10 15 20 BATTERY VOLTAGE (V) 25 30 40071 G08 40071f 5 LTC4007-1 TYPICAL PERFOR A CE CHARACTERISTICS Efficiency at 19VDC VIN 100 16.8V 95 12.6V EFFICIENCY (%) 90 EFFICIENCY (%) 85 80 75 0.50 1.00 1.50 2.00 2.50 CHARGE CURRENT (A) 3.00 PI FU CTIO S ACP(Pin 1): Open-Drain output to indicate if the AC adapter voltage is adequate for charging. This pin is pulled low by an internal N-channel MOSFET if DCIN is below BAT. A pull-up resistor is required. The pin is capable of sinking at least 100A. RT (Pin 2): Timer Resistor. The timer period is set by placing a resistor, RRT , to GND. This resistor is always required. The timer period is tTIMER = (1hour * RRT/154K). If this resistor is not present, the charger will not start. FAULT (Pin 3): Active low open-drain output that indicates charger operation has stopped due to a low-battery conditioning error, or that charger operation is suspended due to the thermistor exceeding allowed values. A pull-up resistor is required if this function is used. The pin is capable of sinking at least 100A. GND (Pin 4): Ground for Low Power Circuitry. 3C4C (Pin 5): Select 3-cell or 4-cell float voltage by connecting this pin to GND or open, respectively. Internal 14A pull-up to 5.3V. This pin can also be driven with open-collector/drain logic levels. High: 4 cell. Low: 3 cell. LOBAT (Pin 6): Low-Battery Indicator. Active low digital output. Internal 10A pull-up to 3.5V. If the battery voltage is below 3.25V/cell (or 3.173V/cell for 4.1V chemistry batteries) LOBAT will be low. The pin is capable of sinking at least 100A. If VLOGIC is greater than 3.3V, add an external pull-up. NTC (Pin 7): A thermistor network is connected from NTC to GND. This pin determines if the battery temperature is safe for charging. The charger and timer are suspended and the FAULT pin is driven low if the thermistor indicates a temperature that is unsafe for charging. The thermistor function may be disabled with a 300k to 500k resistor from DCIN to NTC. ITH (Pin 8): Control Signal of the Inner Loop of the Current Mode PWM. Higher ITH voltage corresponds to higher charging current in normal operation. A 6k resistor, in series with a capacitor of at least 0.1F to GND provides loop compensation. Typical full-scale output current is 40A. Nominal voltage range for this pin is 0V to 3V. 40071f 6 UW Efficiency at 12.6V with 15VDC VIN 100 95 90 85 80 75 0.50 1.00 1.50 2.00 2.50 CHARGE CURRENT (A) 3.00 40071 G10 40071 G11 U U U LTC4007-1 PI FU CTIO S PROG (Pin 9): Current Programming/Monitoring Input/ Output. An external resistor to GND programs the peak charging current in conjunction with the current sensing resistor. The voltage at this pin provides a linear indication of charging current. Peak current is equivalent to 1.19V. Zero current is approximately 0.3V. A capacitor from PROG to ground is required to filter higher frequency components. The maximum resistance to ground is 100k. Values higher than 100k can cause the charger to shut down. ICL (Pin 10): Input Current Limit Indicator. Active low digital output. Internal 10A pull-up to 3.5V. Pulled low if the charger current is being reduced by the input current limiting function. The pin is capable of sinking at least 100A. If VLOGIC is greater than 3.3V, add an external pull-up. CSP (Pin 11): Current Amplifier CA1 Input. The CSP and BAT pins measure the voltage across the sense resistor, RSENSE, to provide the instantaneous current signals required for both peak and average current mode operation. BAT (Pin 12): Battery Sense Input and the Negative Reference for the Current Sense Resistor. A precision internal resistor divider sets the final float potential on this pin. The resistor divider is disconnected during shutdown. CHEM (Pin 13):Select 4.1V or 4.2V cell chemistry by connecting the pin to GND or open, respectively. Internal 14A pull-up to 5.3V. Can also be driven with opencollector/drain logic levels. FLAG (Pin 14): Active low open-drain output that indicates when charging current has declined to 10% of maximum programmed current. A pull-up resistor is required if this function is used. The pin is capable of sinking at least 100A. CLP (Pin 15): Positive input to the supply current limiting amplifier, CL1. The threshold is set at 100mV above the voltage at the CLN pin. When used to limit supply current, a filter is needed to filter out the switching noise. If no current limit function is desired, connect this pin to CLN. CLN (Pin 16): Negative Reference for the Input Current Limit Amplifier, CL1. This pin also serves as the power supply for the IC. A 10F to 22F bypass capacitor should be connected as close as possible to this pin. TGATE (Pin 17): Drives the top external P-channel MOSFET of the battery charger buck converter. PGND (Pin 18): High Current Ground Return for the BGATE Driver. NC (Pin 19): No Connect. BGATE (Pin 20): Drives the bottom external N-channel MOSFET of the battery charger buck converter. INFET (Pin 21): Drives the Gate of the External Input PFET. SHDN (Pin 22): Charger is shut down and timer is reset when this pin is HIGH. Internal 10A pull-up to 3.5V. This pin can also be used to reset the charger by applying a positive pulse that is a minimum of 0.1s long. DCIN (Pin 23): External DC Power Source Input. Bypass this pin with at least 0.01F. See Applications Information. CHG (Pin 24): Charge Status Output. When the battery is being charged, the CHG pin is pulled low by an internal N-channel MOSFET. Internal 10A pull-up to 3.5V. If VLOGIC is greater than 3.3V, add an external pull-up. The timer function can be defeated by forcing this pin below 1V (or connecting it to GND). Exposed Pad (Pin 25): The exposed pad, GND and PGND should be connected together with a low ohmic connection. U U U 40071f 7 LTC4007-1 BLOCK DIAGRA 0.1F VIN DCIN INFET 23 5.8V 21 Q3 ACP 1 SHDN 22 FAULT 3 TBAD THERMISTOR 7 TIMER/CONTROLLER OSCILLATOR 2 FLAG 14 35mV GND C/10 3C4C 5 MUX CHEM 13 12 BAT 3.01k + LOBAT 6 CA1 11 CSP 921mV gm = 1m EA 1.19V - + - 15 100mV 16 - CL1 gm = 1.4m RCL 15nF CLN + DCIN OSCILLATOR WATCHDOG DETECT tOFF gm = 1m ICL 10 20F + OV 1.28V /5 BUFFERED ITH - CLN Q1 17 Q R BGATE PGND CHARGE ICMP Q2 20 18 PWM LOGIC IREV L1 + 8 - + TGATE S 5k CLP - CA2 + - 17mV 9 PROG 0.0047F RPROG 26.7k 40071 BD - + - 4 11.67A 1.19V ITH 6K 0.12F -+ - + + W CLN 24 CHG RT RRT NTC 32.4k 10k NTC 0.47F 397mV RSENSE 3.01k 20F 9k 8 40071f LTC4007-1 TEST CIRCUIT LTC4007-1 13 CHEM DIVIDER/ MUX VREF + EA 5 3C4C - CSP 12 BAT 8 ITH 11 + LT1055 - 40071 TC 0.6V OPERATIO Overview The LTC4007-1 is a synchronous current mode PWM step-down (buck) switcher battery charger controller. The charge current is programmed by the combination of a program resistor (RPROG) from the PROG pin to ground and a sense resistor (RSENSE) between the CSP and BAT pins. The final float voltage is programmed to one of four values (12.3V, 12.6V, 16.4V, 16.8V) with 1% maximum accuracy using pins 3C4C and CHEM. Charging begins when the potential at the DCIN pin rises above the voltage at BAT (and the UVLO voltage) and the SHDN pin is low; the CHG pin is set low. At the beginning of the charge cycle, if the cell voltage is below 3.25V (3.173V if CHEM is low), the LOBAT pin will be low. The LOBAT indicator can be used to reduce the charging current to a low value, typically 10% of full scale. If the cell voltage stays below 3.25V for 25% of the total charge time, the charge sequence will be terminated immediately and the FAULT pin will be set low. An external thermistor network is sampled at regular intervals. If the thermistor value exceeds design limits, charging is suspended and the FAULT pin is set low. If the thermistor value returns to an acceptable value, charging resumes and the FAULT pin is set high. An external resistor on the RT pin sets the total charge time. The timer can be defeated by forcing the CHG pin to a low voltage. As the battery approaches the final float voltage, the charge current will begin to decrease. When the current U drops to 10% of the full-scale charge current, an internal C/10 comparator will indicate this condition by latching the FLAG pin low. The charge timer is also reset to 1/4 of the total charge time when FLAG goes low. If this condition is caused by an input current limit condition, described below, then the FLAG indicator will be inhibited. When a time-out occurs, charging is terminated immediately and the CHG pin is forced to a high impedance state. To restart the charge cycle manually, simply remove the input voltage and reapply it, or set the SHDN pin high momentarily. When the input voltage is not present, the charger goes into a sleep mode, dropping battery current drain to 15A. This greatly reduces the current drain on the battery and increases the standby time. The charger is inhibited any time the SHDN pin is high. Input FET The input FET circuit performs two functions. It enables the charger if the input voltage is higher than the CLN pin and provides the logic indicator of AC present on the ACP pin. It controls the gate of the input FET to keep a low forward voltage drop when charging and also prevents reverse current flow through the input FET. If the input voltage is less than VCLN, it must go at least 170mV higher than VCLN to activate the charger. When this occurs the ACP pin is released and pulled up with an external load to indicate that the adapter is present. The 40071f 9 LTC4007-1 OPERATIO NUMBER 1 2 3 FROM STATE Any Table 1. Truth Table for LTC4007-1 Operation (Supplemental) TO STATE MSD MODE Shut Down by Low Adapter Voltage Charger Shutdown Shut Down by Undervoltage Lockout DCIN 4 MSD SD SD, SD CONDITION, CHARGE SD CONDITION Start Conditioning a Depleted Battery 5 CONDITION CONDITION Input Current Limited Condition Charging CONDITION CONDITION Conditioning a Depleted Battery CONDITION CONDITION Timer Defeated (Low Battery Conditioning Still Functional) CONDITION SD Charger Paused Due to Thermistor Out of Range CONDITION SD Timeout in CONDITION Mode CONDITION SD Shut Down by ACP/SHDN Pin CONDITION CHARGE Start Normal Charging CHARGE CHARGE Timer Defeated (Low Battery Conditioning Still Functional) Top-Off Charging C/10 Latch is SET when Battery Current Is Less than 10% of Programmed Current Top-Off Charging Input Current Limited Charging Charger Paused Due to Thermistor Out of Range Shut Down by ACP/SHDN Pin Terminated by LowBattery Fault (Note 1) Terminates After T/4 Terminates After T 6 7 8 9 10 11 12 13 14 CHARGE CHARGE 15 16 17 CHARGE CHARGE CHARGE 18 19 20 21 CHARGE CHARGE CHARGE CHARGE *Most probable condition Note 1: If a depleted battery is inserted while the charger is in this state, the charger must be reset to initiate charging. Note 2: See section on "Adapter Limiting". 10 U <3.25V/Cell >BAT <3.25V/Cell >BAT <3.25V/Cell >BAT <3.25V/Cell >BAT >BAT >BAT >BAT >BAT <3.25V/Cell <3.25V/Cell <3.25V/Cell >3.25V/Cell >3.25V/Cell 0 10% Programmed Current <10% Programmed Current (Note 2) 10% Programmed Current 10% Programmed Current OFF OFF OFF Programmed Current Programmed Current 0 1 Programmed Current Programmed Current HIGH LOW HIGH Running LOW HIGH Running LOW HIGH Ignored Forced LOW LOW (Faulted) HIGH (Faulted) HIGH HIGH HIGH Forced LOW HIGH HIGH Paused >T/4 Reset Running Ignored Forced LOW LOW 25A CHARGE CHARGE >BAT >BAT >3.25V/Cell >3.25V/Cell HIGH HIGH Running Reset CHARGE CHARGE SD >BAT >BAT >BAT >3.25V/Cell >3.25V/Cell >3.25V/Cell 1 Programmed Current 40071f LTC4007-1 OPERATIO U LTC4007-1: State Diagram MASTER SHUTDOWN 2 1 ANY SHUTDOWN 4 3, 8, 9, 10 3, 17, 18, 19, 20, 21 5, 6, 7 CONDITION 11 CHARGE 12, 13, 14, 15, 16 40071 TBL01 gate of the input FET is driven to a voltage sufficient to keep a low forward voltage drop from drain to source. If the voltage between DCIN and CLN drops to less than 25mV, the input FET is turned off slowly. If the voltage between DCIN and CLN is ever less than - 25mV, then the input FET is turned off in less than 10s to prevent significant reverse current from flowing in the input FET. In this condition, the ACP pin is driven low and the charger is disabled. Battery Charger Controller The LTC4007-1 charger controller uses a constant offtime, current mode step-down architecture. During normal operation, the top MOSFET is turned on each cycle when the oscillator sets the SR latch and turned off when the main current comparator ICMP resets the SR latch. While the top MOSFET is off, the bottom MOSFET is turned on until either the inductor current trips the current comparator IREV or the beginning of the next cycle. The oscillator uses the equation: to set the bottom MOSFET on time. The result is a nearly constant switching frequency over a wide input/output voltage range. This activity is diagrammed in Figure 1. The peak inductor current, at which ICMP resets the SR latch, is controlled by the voltage on ITH. ITH is in turn controlled by several loops, depending upon the situation at hand. The average current control loop converts the voltage between CSP and BAT to a representative current. Error amp CA2 compares this current against the desired current programmed by RPROG at the PROG pin and OFF TGATE ON ON BGATE OFF TRIP POINT SET BY ITH VOLTAGE INDUCTOR CURRENT 40071 F01 tOFF tOFF = VDCIN - VBAT VDCIN * fOSC Figure 1 40071f 11 LTC4007-1 OPERATIO adjusts ITH until: VREF V - V + 11.67A * 3.01k = CSP BAT RPROG 3.01k therefore, V 3.01k ICHARGE(MAX) = REF - 11.67A * RPROG RSENSE The voltage at BAT is divided down by an internal resistor divider and is used by error amp EA to decrease ITH if the divider voltage is above the 1.19V reference. When the charging current begins to decrease, the voltage at PROG will decrease in direct proportion. The voltage at PROG is then given by: VPROG = (ICHARGE * RSENSE + 11.67A * 3.01k) * RPROG 3.01k VPROG is plotted in Figure 2. The amplifier CL1 monitors and limits the input current, normally from the AC adapter to a preset level (100mV/ RCL). At input current limit, CL1 will decrease the ITH voltage, thereby reducing charging current. The ICL indicator output will go low when this condition is detected and the FLAG indicator will be inhibited if it is not already LOW. 1.2 1.0 0.8 1.19V VPROG (V) 0.6 0.4 0.309V 0.2 0 0 60 80 20 40 ICHARGE (% OF MAXIMUM CURRENT) Figure 2. VPROG vs ICHARGE 12 U If the charging current decreases below 10% to 15% of programmed current while engaged in input current limiting, BGATE will be forced low to prevent the charger from discharging the battery. Audible noise can occur in this mode of operation. An overvoltage comparator guards against voltage transient overshoots (>7% of programmed value). In this case, both MOSFETs are turned off until the overvoltage condition is cleared. This feature is useful for batteries which "load dump" themselves by opening their protection switch to perform functions such as calibration or pulse mode charging. PWM Watchdog Timer There is a watchdog timer that observes the activity on the BGATE and TGATE pins. If TGATE stops switching for more than 40s, the watchdog activates and turns off the top MOSFET for about 400ns. The watchdog engages to prevent very low frequency operation in dropout--a potential source of audible noise when using ceramic input and output capacitors. Charger Start-Up When the charger is enabled, it will not begin switching until the ITH voltage exceeds a threshold that assures initial current will be positive. This threshold is 5% to 15% of the maximum programmed current. After the charger begins switching, the various loops will control the current at a level that is higher or lower than the initial current. The duration of this transient condition depends upon the loop compensation, but is typically less than 100s. Thermistor Detection The thermistor detection circuit is shown in Figure 3. It requires an external resistor and capacitor in order to function properly. The thermistor detector performs a sample-and-hold function. An internal clock, whose frequency is determined by 100 40071 F02 40071f LTC4007-1 OPERATIO the timing resistor connected to RT, keeps switch S1 closed to sample the thermistor: tSAMPLE = 127.5 * 20 * RRT * 17.5pF = 13.8ms, for RRT = 309k The external RC network is driven to approximately 4.5V and settles to a final value across the thermistor of: VRTH(FINAL) = 4.5V * RTH RTH + R9 This voltage is stored by C7. Then the switch is opened for a short period of time to read the voltage across the thermistor. LTC4007-1 U tHOLD = 10 * RRT * 17.5pF = 54s, for RRT = 309k When the tHOLD interval ends the result of the thermistor testing is stored in the D flip-flop (DFF). If the voltage at NTC is within the limits provided by the resistor divider feeding the comparators, then the NOR gate output will be low and the DFF will set TBAD to zero and charging will continue. If the voltage at NTC is outside of the resistor divider limits, then the DFF will set TBAD to one, the charger will be shut down, FAULT pin is set low and the timer will be suspended until TBAD returns to zero (see Figure 4). CLK R9 32.4k 7 RTH 10k NTC C7 0.47F - NTC S1 + ~4.5V 60k + - - + 15k D C 40071 F03 45k Q TBAD Figure 3 CLK (NOT TO SCALE) tHOLD tSAMPLE VOLTAGE ACROSS THERMISTOR VNTC COMPARATOR HIGH LIMIT COMPARATOR LOW LIMIT 40071 F04 Figure 4 40071f 13 LTC4007-1 APPLICATIO S I FOR ATIO Battery Detection It is generally not good practice to connect a battery while the charger is running. The timer is in an unknown state and the charger could provide a large surge current into the battery for a brief time. The Figure 5 circuit keeps the charger shut down and the timer reset while a battery is not connected. LTC4007-1 ADAPTER POWER SWITCH CLOSED WHEN BATTERY CONNECTED 23 DCIN 22 SHDN 40071 F05 Figure 5 Charger Current Programming The basic formula for charging current is: ICHARGE(MAX) = VREF = 1.19V VREF * 3.01k / RPROG - 0.035V RSENSE This leaves two degrees of freedom: RSENSE and RPROG. The 3.01k input resistors must not be altered since internal currents and voltages are trimmed for this value. Pick RSENSE by setting the average voltage between CSP and BAT to be close to 100mV during maximum charger current. Then RPROG can be determined by solving the above equation for RPROG. RPROG = VREF * 3.01k RSENSE * ICHARGE(MAX) + 0.035V RSENSE () 1% 0.100 0.050 0.033 0.025 RSENSE (W) 0.25 0.25 0.5 0.5 RPROG (k) 1% 26.7 26.7 26.7 26.7 Table 2. Recommended RSNS and RPROG Resistor Values IMAX (A) 1.0 2.0 3.0 4.0 14 U LTC4007-1 PROG 9 RZ 102k RPROG 5V 0V Q1 2N7002 40071 F06 W UU CPROG Figure 6. PWM Current Programming Charging current can be programmed by pulse width modulating RPROG with a switch Q1 to RPROG at a frequency higher than a few kHz (Figure 6). CPROG must be increased to reduce the ripple caused by the RPROG switching. The compensation capacitor at ITH will probably need to be increased also to improve stability and prevent large overshoot currents during start-up conditions. Charging current will be proportional to the duty cycle of the switch with full current at 100% duty cycle and zero current when Q1 is off. Maintaining C/10 Accuracy The C/10 comparator threshold that drives the FLAG pin has a fixed threshold of approximately VPROG = 400mV. This threshold works well when RPROG is 26.7k, but will not yield a 10% charging current indication if RPROG is a different value. There are situations where a standard value of RSENSE will not allow the desired value of charging current when using the preferred RPROG value. In these cases, where the full-scale voltage across RSENSE is within 20mV of the 100mV full-scale target, the input resistors connected to CSP and BAT can be adjusted to provide the desired maximum programming current as well as the correct FLAG trip point. For example, the desired max charging current is 2.5A but the best RSENSE value is 0.033. In this case, the voltage across RSENSE at maximum charging current is only 82.5mV, normally RPROG would be 30.1k but the nominal FLAG trip point is only 5% of maximum charging current. If the input resistors are reduced by the same amount as 40071f LTC4007-1 APPLICATIO S I FOR ATIO the full-scale voltage is reduced then, R4 = R5 = 2.49k and RPROG = 26.7k, the maximum charging current is still 2.5A but the FLAG trip point is maintained at 10% of full scale. There are other effects to consider. The voltage across the current comparator is scaled to obtain the same values as the 100mV sense voltage target, but the input referred sense voltage is reduced, causing some careful consideration of the ripple current. Input referred maximum comparator threshold is 117mV, which is the same ratio of 1.4x the DC target. Input referred IREV threshold is scaled back to -24mV. The current at which the switcher starts will be reduced as well so there is some risk of boost activity. These concerns can be addressed by using a slightly larger inductor to compensate for the reduction of tolerance to ripple current. Charger Voltage Programming Pins CHEM and C3C4 are used to program the charger final output voltage. The CHEM pin programs Li-Ion battery chemistry for 4.1V/cell (low) or 4.2V/cell (high). The C3C4 pin selects either 3 series cells (low) or 4 series cells (high). It is recommended that these pins be shorted to ground (logic low) or left open (logic high) to effect the desired logic level. Use open-collector or open-drain outputs when interfacing to the CHEM and 3C4C pins from a logic control circuit. Table 3. Charger Voltage Programming VFINAL (V) 12.3 12.6 16.4 16.8 3C4C LOW LOW HIGH HIGH CHEM LOW HIGH LOW HIGH tTIMER (MINUTES) Setting the Timer Resistor The charger termination timer is designed for a range of 1hour to 3 hour with a 15% uncertainty. The timer is programmed by the resistor RRT using the following equation: tTIMER = 10 * 227 * RRT * 17.5pF (seconds) U 500 450 400 350 300 250 200 150 100 50 0 100 300 500 700 900 RRT (k) 1100 1300 40071 F07 W UU Figure 7. tTIMER vs RRT It is important to keep the parasitic capacitance on the RT pin to a minimum. The trace connecting RT to RRT should be as short as possible. Soft-Start The LTC4007-1 is soft started by the 0.12F capacitor on the ITH pin. On start-up, ITH pin voltage will rise quickly to 0.5V, then ramp up at a rate set by the internal 40A pullup current and the external capacitor. Battery charging current starts ramping up when ITH voltage reaches 0.8V and full current is achieved with ITH at 2V. With a 0.12F capacitor, time to reach full charge current is about 2ms and it is assumed that input voltage to the charger will reach full value in less than 2ms. The capacitor can be increased up to 1F if longer input start-up times are needed. Input and Output Capacitors The input capacitor (C2) is assumed to absorb all input switching ripple current in the converter, so it must have adequate ripple current rating. Worst-case RMS ripple current will be equal to one half of output charging current. Actual capacitance value is not critical. Solid tantalum low ESR capacitors have high ripple current rating in a relatively small surface mount package, but caution must be 40071f 15 LTC4007-1 APPLICATIO S I FOR ATIO used when tantalum capacitors are used for input or output bypass. High input surge currents can be created when the adapter is hot-plugged to the charger or when a battery is connected to the charger. Solid tantalum capacitors have a known failure mechanism when subjected to very high turn-on surge currents. Only Kemet T495 series of "Surge Robust" low ESR tantalums are rated for high surge conditions such as battery to ground. The relatively high ESR of an aluminum electrolytic for C1, located at the AC adapter input terminal, is helpful in reducing ringing during the hot-plug event. Refer to AN88 for more information. Highest possible voltage rating on the capacitor will minimize problems. Consult with the manufacturer before use. Alternatives include new high capacity ceramic (at least 20F) from Tokin, United Chemi-Con/Marcon, et al. Other alternative capacitors include OS-CON capacitors from Sanyo. The output capacitor (C3) is also assumed to absorb output switching current ripple. The general formula for capacitor current is: V 0.29(VBAT ) 1 - BAT VDCIN = (L1)( f) IRMS For example: VDCIN = 19V, VBAT = 12.6V, L1 = 10H, and f = 300kHz, IRMS = 0.41A. EMI considerations usually make it desirable to minimize ripple current in the battery leads, and beads or inductors may be added to increase battery impedance at the 300kHz switching frequency. Switching ripple current splits between the battery and the output capacitor depending on the ESR of the output capacitor and the battery impedance. If the ESR of C3 is 0.2 and the battery impedance 16 U is raised to 4 with a bead or inductor, only 5% of the current ripple will flow in the battery. Inductor Selection Higher operating frequencies allow the use of smaller inductor and capacitor values. A higher frequency generally results in lower efficiency because of MOSFET gate charge losses. In addition, the effect of inductor value on ripple current and low current operation must also be considered. The inductor ripple current IL decreases with higher frequency and increases with higher VIN. IL = V 1 VOUT 1- OUT ( f)(L) VIN W UU Accepting larger values of IL allows the use of low inductances, but results in higher output voltage ripple and greater core losses. A reasonable starting point for setting ripple current is IL = 0.4(IMAX). In no case should IL exceed 0.6(IMAX) due to limits imposed by IREV and CA1. Remember the maximum IL occurs at the maximum input voltage. In practice 10H is the lowest value recommended for use. Lower charger currents generally call for larger inductor values. Use Table 4 as a guide for selecting the correct inductor value for your application. Table 4 MAX AVERAGE CURRENT (A) 1 1 2 2 3 3 4 4 INPUT VOLTAGE (V) 20 >20 20 >20 20 >20 20 >20 MINIMUM INDUCTOR VALUE (H) 40 20% 56 20% 20 20% 30 20% 15 20% 20 20% 10 20% 15 20% 40071f LTC4007-1 APPLICATIO S I FOR ATIO Charger Switching Power MOSFET and Diode Selection Two external power MOSFETs must be selected for use with the charger: a P-channel MOSFET for the top (main) switch and an N-channel MOSFET for the bottom (synchronous) switch. The peak-to-peak gate drive levels are set internally. This voltage is typically 6V. Consequently, logic-level threshold MOSFETs must be used. Pay close attention to the BVDSS specification for the MOSFETs as well; many of the logic level MOSFETs are limited to 30V or less. Selection criteria for the power MOSFETs include the "ON" resistance RDS(ON), total gate capacitance QG, reverse transfer capacitance CRSS, input voltage and maximum output current. The charger is operating in continuous mode at moderate to high currents so the duty cycles for the top and bottom MOSFETs are given by: Main Switch Duty Cycle = VOUT/VIN Synchronous Switch Duty Cycle = (VIN - VOUT)/VIN. The MOSFET power dissipations at maximum output current are given by: PMAIN = VOUT/VIN(IMAX)2(1 + T)RDS(ON) + k(VIN)2(IMAX)(CRSS)(fOSC) PSYNC = (VIN - VOUT)/VIN(IMAX)2(1 + T)RDS(ON) Where T is the temperature dependency of RDS(ON) and k is a constant inversely related to the gate drive current. Both MOSFETs have I2R losses while the PMAIN equation includes an additional term for transition losses, which are highest at high input voltages. For VIN < 20V the high current efficiency generally improves with larger MOSFETs, while for VIN > 20V the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CRSS actually provides higher efficiency. The synchronous MOSFET losses are greatest at high input voltage or during a short circuit when the duty cycle in this U switch in nearly 100%. The term (1 + T) is generally given for a MOSFET in the form of a normalized RDS(ON) vs temperature curve, but = 0.005/C can be used as an approximation for low voltage MOSFETs. CRSS = QGD/VDS is usually specified in the MOSFET characteristics. The constant k = 2 can be used to estimate the contributions of the two terms in the main switch dissipation equation. If the charger is to operate in low dropout mode or with a high duty cycle greater than 85%, then the topside P-channel efficiency generally improves with a larger MOSFET. Using asymmetrical MOSFETs may achieve cost savings or efficiency gains. The Schottky diode D1, shown in the Typical Application on the back page, conducts during the dead-time between the conduction of the two power MOSFETs. This prevents the body diode of the bottom MOSFET from turning on and storing charge during the dead-time, which could cost as much as 1% in efficiency. A 1A Schottky is generally a good size for 4A regulators due to the relatively small average current. Larger diodes can result in additional transition losses due to their larger junction capacitance. The diode may be omitted if the efficiency loss can be tolerated. Calculating IC Power Dissipation The power dissipation of the LTC4007-1 is dependent upon the gate charge of the top and bottom MOSFETs (QG1 & QG2 respectively) The gate charge is determined from the manufacturer's data sheet and is dependent upon both the gate voltage swing and the drain voltage swing of the MOSFET. Use 6V for the gate voltage swing and VDCIN for the drain voltage swing. PD = VDCIN * (fOSC (QG1 + QG2) + IQ) Example: VDCIN = 19V, fOSC = 345kHz, QG1 = QG2 = 15nC, IQ = 5mA PD = 292mW 40071f W UU 17 LTC4007-1 APPLICATIO S I FOR ATIO Adapter Limiting An important feature of the LTC4007-1 is the ability to automatically adjust charging current to a level which avoids overloading the wall adapter. This allows the product to operate at the same time that batteries are being charged without complex load management algorithms. Additionally, batteries will automatically be charged at the maximum possible rate of which the adapter is capable. This feature is created by sensing total adapter output current and adjusting charging current downward if a preset adapter current limit is exceeded. True analog control is used, with closed-loop feedback ensuring that adapter load current remains within limits. Amplifier CL1 in Figure 8 senses the voltage across RCL, connected between the CLP and CLN pins. When this voltage exceeds 100mV, the amplifier will override programmed charging current to limit adapter current to 100mV/RCL. A lowpass filter formed by 5k and 15nF is required to eliminate switching noise. If the current limit is not used, CLP should be connected to CLN. Note that the ICL pin will be asserted when the voltage across RCL is 93mV, before the adapter limit regulation threshold. LTC4007-1 100mV - CL1 + CLP 15 15nF 5k AC ADAPTER INPUT VIN + CLN 16 100mV ADAPTER CURRENT LIMIT RCL* + CIN *RCL = Figure 8. Adapter Current Limiting Setting Input Current Limit To set the input current limit, you need to know the minimum wall adapter current rating. Subtract 7% for the 18 U input current limit tolerance and use that current to determine the resistor value. RCL = 100mV/ILIM ILIM = Adapter Min Current - (Adapter Min Current * 7%) Table 5. Common RCL Resistor Values ADAPTER RATING (A) 1.5 1.8 2 2.3 2.5 2.7 3 RCL VALUE* () 1% 0.06 0.05 0.045 0.039 0.036 0.033 0.03 RCL POWER DISSIPATION (W) 0.135 0.162 0.18 0.206 0.225 0.241 0.27 RCL POWER RATING (W) 0.25 0.25 0.25 0.25 0.5 0.5 0.5 * Values shown above are rounded to nearest standard value. W UU As is often the case, the wall adapter will usually have at least a +10% current limit margin and many times one can simply set the adapter current limit value to the actual adapter rating (see Table 5). Designing the Thermistor Network There are several networks that will yield the desired function of voltage vs temperature needed for proper operation of the thermistor. The simplest of these is the voltage divider shown in Figure 9. Unfortunately, since the HIGH/LOW comparator thresholds are fixed internally, there is only one thermistor type that can be used in this network; the thermistor must have a HIGH/LOW resistance ratio of 1:7. If this happy circumstance is true for you, then simply set R9 = RTH(LOW). LTC4007-1 NTC 7 C7 RTH 40071 F09 40071 F08 R9 Figure 9. Voltage Divider Thermistor Network 40071f LTC4007-1 APPLICATIO S I FOR ATIO LTC4007-1 NTC 7 C7 R9A RTH 40071 F10 R9 Figure 10. General Thermistor Network If you are using a thermistor that doesn't have a 1:7 HIGH/ LOW ratio, or you wish to set the HIGH/LOW limits to different temperatures, then the more generic network in Figure 10 should work. Once the thermistor, RTH, has been selected and the thermistor value is known at the temperature limits, then resistors R9 and R9A are given by: For NTC thermistors: R9 = 6 RTH(LOW) * RTH(HIGH)/(RTH(LOW) - RTH(HIGH)) R9A = 6 RTH(LOW) * RTH(HIGH)/(RTH(LOW) - 7 * RTH(HIGH)) Where RTH(LOW) > 7 * RTH(HIGH) For PTC thermistors: R9 = 6 RTH(LOW) * RTH(HIGH)/(RTH(HIGH) - RTH(LOW)) R9A = 6 RTH(LOW) * RTH(HIGH)/(RTH(HIGH) - 7 * RTH(LOW)) Where RTH(HIGH) > 7 * RTH(LOW) Example #1: 10k NTC with custom limits TLOW = 0C, THIGH = 50C RTH = 10k at 25C, RTH(LOW) = 32.582k at 0C RTH(HIGH) = 3.635k at 50C R9 = 24.55k 24.3k (nearest 1% value) R9A = 99.6k 100k (nearest 1% value) U Example #2: 100k NTC TLOW = 5C, THIGH = 50C RTH = 100k at 25C, RTH(LOW) = 272.05k at 5C RTH(HIGH) = 33.195k at 50C R9 = 226.9k 226k (nearest 1% value) R9A = 1.365M 1.37M (nearest 1% value) Example #3: 22k PTC TLOW = 0C, THIGH = 50C RTH = 22k at 25C, RTH(LOW) = 6.53k at 0C RTH(HIGH) = 61.4k at 50C R9 = 43.9k 44.2k (nearest 1% value) R9A = 154k Sizing the Thermistor Hold Capacitor During the hold interval, C7 must hold the voltage across the thermistor relatively constant to avoid false readings. A reasonable amount of ripple on NTC during the hold interval is about 10mV to 15mV. Therefore, the value of C7 is given by: C7 = tHOLD/(R9/7 * -ln(1 - 8 * 15mV/4.5V)) = 10 * RRT * 17.5pF/(R9/7 * - ln(1 - 8 * 15mV/4.5V) Example: R9 = 24.3k RRT = 309k (~2 hour timer) C7 = 0.57F 0.56F (nearest value) 40071f W UU 19 LTC4007-1 APPLICATIO S I FOR ATIO Disabling the Thermistor Function If the thermistor is not needed, connecting a resistor between DCIN and NTC will disable it. The resistor should be sized to provide at least 10A with the minimum voltage applied to DCIN and 10V at NTC. Do not exceed 30A. Generally, a 301k resistor will work for DCIN less than 15V. A 499k resistor is recommended for DCIN between 15V and 24V. Conditioning Depleted Batteries Severely depleted batteries, with less than 3.25V/cell, should be conditioned with a trickle charge to prevent possible damage. This trickle charge is typically 10% of the 1C rate of the battery. The LTC4007-1 can automatically trickle charge depleted batteries using the circuit in Figure 11. If the battery voltage is less than 3.25V/cell (3.173V/cell if CHEM is low) then the LOBAT indicator will be low and Q4 is off. This programs the charging current with RPROG = R6 + R14. Charging current is approximately 300mA. When the cell voltage becomes greater than 3.25V the LOBAT indicator goes high, Q4 shorts out R13, then RPROG = R6. Charging current is then equal to 3A. PCB Layout Considerations For maximum efficiency, the switch node rise and fall times should be minimized. To prevent magnetic and electrical field radiation and high frequency resonant problems, proper layout of the components connected to the IC is essential. (See Figure 12.) Here is a PCB layout priority list for proper layout. Layout the PCB using this specific order. 20 U General Rules 1. Input capacitors need to be placed as close as possible to switching FET's supply and ground connections. Shortest copper trace connections possible. These parts must be on the same layer of copper. Vias must not be used to make this connection. 2. The control IC needs to be close to the switching FET's gate terminals. Keep the gate drive signals short for a clean FET drive. This includes IC supply pins that connect to the switching FET source pins. The IC can be placed on the opposite side of the PCB relative to above. 3. Place inductor input as close as possible to switching FET's output connection. Minimize the surface area of this trace. Make the trace width the minimum amount needed to support current--no copper fills or pours. Avoid running the connection using multiple layers in parallel. Minimize capacitance from this node to any other trace or plane. 4. Place the output current sense resistor right next to the inductor output but oriented such that the IC's current sense feedback traces going to resistor are not long. The feedback traces need to be routed together as a single pair on the same layer at any given time with smallest trace spacing possible. Locate any filter component on these traces next to the IC and not at the sense resistor location. 5. Place output capacitors next to the sense resistor output and ground. 6. Output capacitor ground connections need to feed into same copper that connects to the input capacitor ground before tying back into system ground. 40071f W UU LTC4007-1 APPLICATIO S I FOR ATIO General Rules (Continued) 7. Connection of switching ground to system ground or internal ground plane should be single point. If the system has an internal system ground plane, a good way to do this is to cluster vias into a single star point to make the connection. 8. Route analog ground as a trace tied back to IC ground (analog ground pin if present) before connecting to any other ground. Avoid using the system ground plane. CAD trick: make analog ground a separate ground net and use a 0 resistor to tie analog ground to system ground. 9. A good rule of thumb for via count for a given high current path is to use 0.5A per via. Be consistent. U 10. If possible, place all the parts listed above on the same PCB layer. 11. Copper fills or pours are good for all power connections except as noted above in Rule 3. You can also use copper planes on multiple layers in parallel too--this helps with thermal management and lower trace inductance improving EMI performance further. 12. For best current programming accuracy provide a Kelvin connection from RSENSE to CSP and BAT. See Figure 12 as an example. It is important to keep the parasitic capacitance on the RT, CSP and BAT pins to a minimum. The traces connecting these pins to their respective resistors should be as short as possible. 40071f W UU 21 LTC4007-1 APPLICATIO S I FOR ATIO U Q3 INPUT SWITCH C1 0.1F * R10 100k LOBAT ICL ACP SHDN FAULT CHG FLAG R9 32.4k 1% R11 100k R12 100k * 3C4C CHEM LOBAT ICL ACP SHDN FAULT CHG FLAG NTC C7 0.47F RT 309k 1% RT DCIN INFET CLP C4 15nF R1 4.99k 1% RCL 0.033 1% C2 20F Q1 Q2 R4 3.01k 1% R5 3.01k 1% MONITOR (CHARGING CURRENT MONITOR) L1 15H 3A D1 RSENSE 0.033 1% BAT C3 20F SYSTEM LOAD R7 6.04k 1% C6 0.12F C5 0.0047F R14 52.3k 1% R6 26.7k 1% Q4 *PIN OPEN D1: MBRM140T3 Q1: Si4431BDY Q2: FDC645N Q4: 2N7002 OR BSS138 40071 F11 DCIN 0V TO 20V 3A VLOGIC THERMISTOR TIMING RESISTOR (~2 HOURS) Figure 11. Circuit Application (16.8V/3A) to Automatically Trickle Charge Depleted Batteries 22 W UU LTC4007-1 CLN TGATE BGATE PGND CSP BAT PROG ITH GND 40071f LTC4007-1 APPLICATIO S I FOR ATIO SWITCH NODE L1 VBAT HIGH FREQUENCY CIRCULATING PATH DIRECTION OF CHARGING CURRENT VIN C2 D1 C3 Figure 12. High Speed Switching Path PACKAGE DESCRIPTION UFD Package 24-Lead Plastic QFN (4mm x 5mm) (Reference LTC DWG # 05-08-1696) 2.65 0.10 (2 SIDES) 4.00 0.10 (2 SIDES) 0.70 0.05 4.50 0.05 3.10 0.05 2.65 0.05 (2 SIDES) 5.00 0.10 (2 SIDES) PIN 1 TOP MARK (NOTE 6) 3.65 0.10 (2 SIDES) 0.75 0.05 R = 0.115 TYP 23 24 PIN 1 NOTCH R = 0.30 TYP 0.25 0.05 0.50 BSC 3.65 0.05 (2 SIDES) 4.10 0.05 5.50 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS PACKAGE OUTLINE NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X). 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U BAT RSENSE 40071 F13 U W UU 40071 F12 CSP BAT Figure 13. Kelvin Sensing of Charging Current 0.40 0.05 1 2 (UFD25) QFN 0504 0.200 REF 0.00 - 0.05 0.25 0.05 0.50 BSC BOTTOM VIEW--EXPOSED PAD 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 40071f 23 LTC4007-1 TYPICAL APPLICATIO DCIN 0V TO 20V 3A VLOGIC R10 100k LOBAT ICL ACP SHDN FAULT CHG FLAG R9 32.4k 1% R11 100k R12 100k * THERMISTOR 10k NTC C7 0.47F RRT 309k 1% RELATED PARTS PART NUMBER LT 1511 LT1513 LT1571 LTC1628-PG LTC1709 LT1769 LTC1778 LTC1960 LTC3711 LTC4006 (R) DESCRIPTION Constant-Current/Constant-Voltage 3A Battery Charger with Input Current Limiting SEPIC Constant- or Programmable-Current/ Constant-Voltage Battery Charger 1.5A Switching Charger 2-Phase, Dual Synchronous Step-Down Controller 2-Phase, Dual Synchronous Step-Down Controller with VID 2A Switching Battery Charger Wide Operating Range, No RSENSE Synchronous Step-Down Controller Dual Battery Charger/Selector with SPI Interface No RSENSETM Synchronous Step-Down Controller with VID Small, High Efficiency, Fixed Voltage, Lithium-Ion Battery Charger LTC4007 LTC4008 LTC4100 4A High Efficiency, Standalone Li-Ion Battery Charger Complete Charger for 3- or 4-Cell Li-Ion Batteries, AC Adapter Current Limit and Thermistor Sensor, 16-Pin Narrow SSOP Package High Efficiency, Programmable Voltage/Current Battery Charger Smart Battery Charger Controller Constant-Current/Constant-Voltage Switching Regulator, Resistor Voltage/ Current Programming, AC Adapter Current Limit and Thermistor Sensor 100% Compliant SMBus 1.1 Support, VIN: 6.4V to 26V, VDROPOUT = 0.5V, High Efficiency Synchronous Buck Charger 40071f No RSENSE is a trademark of Linear Technology Corporation. 24 Linear Technology Corporation (408) 432-1900 FAX: (408) 434-0507 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com U 12.6V, 4A Li-Ion Battery Charger Q3 INPUT SWITCH C1 0.1F 3C4C CHEM LOBAT ICL ACP SHDN FAULT CHG FLAG NTC RT DCIN INFET CLP C4 15nF R1 4.99k 1% RCL 0.033 1% C2 20F Q1 Q2 R4 3.01k 1% R5 3.01k 1% R7 6.04k 1% C6 0.12F C5 0.0047F RPROG 26.7k 1% CHARGING CURRENT MONITOR *PIN OPEN D1: MBRS130T3 Q1: Si4431BDY Q2: FDC645N 40071 TA02 SYSTEM LOAD RSENSE L1 0.025 10H 4A 1% BAT D1 C3 20F LTC4007-1 CLN TGATE BGATE PGND CSP BAT PROG ITH GND TIMING RESISTOR (~2 HOURS) COMMENTS High Efficiency Current Mode PWM with 4A Internal Switch Charger Input Voltage May Be Higher, Equal to or Lower Than Battery Voltage; Charges Any Number of Cells Up to 20V, 500kHz Switching Frequency 1- or 2-Cell Li-Ion, 500kHz or 200kHz Switching Frequency, Termination Flag Minimizes CIN and COUT, Power Good Output, 3.5V VIN 36V Up to 42A Output, Minimum CIN and COUT, Uses Smallest Components for Intel and AMD Processors Constant-Current/Constant-Voltage Switching Regulator, Input Current Limiting Maximizes Charge Current 2% to 90% Duty Cycle at 200kHz, Stable with Ceramic COUT Simultaneous Charge or Discharge of Two Batteries, DAC Programmable Current and Voltage, Input Current Limiting Maximizes Charge Current 3.5V VIN 36V, 0.925V VOUT 2V, for Transmeta, AMD and Intel Mobile Processors Constant-Current/Constant-Voltage Switching Regulator with Termination Timer, AC Adapter Current Limit and Thermistor Sensor in a Small 16-Pin Package LT/TP 1005 500 * PRINTED IN USA (c) LINEAR TECHNOLOGY CORPORATION 2005 |
Price & Availability of LTC4007EUFD-1
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |